Digital Logic Design Engineer

• Developed and maintained SystemVerilog/UVM testbenches for functional verification of 10+ critical IP cores on production SoCs, including PCI, I2C, UART, and SPI interfaces.
• Created a Perl framework for generating wafer-level and package-level manufacturing test patterns for SerDes and MBIST IP validation on RAD5545 SoCs, ensuring production-quality hardware functionality.
• Collaborated with interns in the development of memory test and repair sequences for SoCs using C++ and JTAG Corelis boundary scan hardware. Used on-chip fuses to enable redundant memory columns and repair memory faults for several devices.
• Presented automated MBIST test insertion methodology research to the Virginia Microelectronics Consortium (VMEC), demonstrating innovation in test automation.
• Served in the onsite Young Professionals and Health & Wellness committees.

Summary

As a Digital Logic Design Engineer at BAE Systems Inc., I worked on critical space technology projects involving ASIC verification and testing. My role encompassed both technical development and leadership responsibilities.

Key Responsibilities

ASIC Verification & Testing:

• Created various UVM test sequences for verifying several protocols on ASICs including PCI, JTAG, and I2C
• Constructed several scripts to automate memory built-in self-test (MBIST) operations and fuse repairs
• Performed design for test pattern generation and bring-up tasks on the RAD5545 single-board computer
• Led VMEC interns in their projects (2018, 2019)
• Conducted MBIST Wafer and Module Testing for RAD5545
• Worked with JTAG Corelis systems
• Performed UVM Verification for UART on RAD510

Leadership & Community:

• Mentored a team of interns in programming software to perform memory test and repair tasks
• Served in the onsite Young Professionals and Health & Wellness committees

VMEC Internship Experience

Prior to my full-time role, I was a Virginia Microelectronics Consortium (VMEC) Intern from May 2017 to December 2017, where I gained:

• Experience documenting and integrating memory built-in self-test (MBIST) systems written in Verilog and VHDL
• Experience modifying and simulating Universal Verification Methodology (UVM) Test Benches