Osaze Shears
Senior FPGA Engineer

Senior FPGA Engineer

USC Information Sciences Institute
Arlington, Virginia
  • Architected and integrated a top-level SoC design using SystemVerilog with JTAG, PLL, SerDes, and custom IP for a homomorphic encryption ASIC. Interfaced memory-mapped control-status registers with AXI4Lite interconnect for external FPGA access.
  • Developed comprehensive FPGA test platforms using Vivado and Vitis across Xilinx Versal, UltraScale+, and Series 7 devices to validate functionality of slices, interconnect, and hard IP blocks. C code developed for MicroBlaze to enable run-time testing.
  • Developed codebase for automating EDA tool build processes and FPGA debugging using Python and TCL. Maintained codebase using GitLab CI/CD flows, merge requests, and issue tracking.
  • Implemented and optimized MobileNet accelerator on Zynq ZCU104 using Xilinx FINN framework, Python, Xilinx HLS, and C. Worked towards energy efficiency and latency improvements for object detection and tracking with the BDD100K dataset.
  • Performed functional verification and debugging of NoC-based ASIC architectures using Xcelium and emulations on VCU128.
  • Collaborated with interns to bring-up a Synopsys HAPS-100 prototyping platform for emulation of ASIC designs.
  • Maintained GitLab Wiki repositories to document workflows, facilitate knowledge sharing, and host project documentation.
  • Performed formal equivalence checking using Synopsys Formality on FPGA netlists generated by Synopsys Synplify and Xilinx Vivado.

Projects